On Mon, Oct 19, 2009 at 07:19:52PM +0200, Johnny Billquist wrote:
Any more 11/70 machines around?
I've got one. Dave McGuire has two.
-brian
--
"Coding in C is like sending a 3 year old to do groceries. You gotta
tell them exactly what you want or you'll end up with a cupboard full of
pop tarts and pancake mix." -- IRC User (http://www.bash.org/?841435)
Sridhar Ayengar wrote:
Johnny Billquist wrote:
Pontus Pihlgren wrote:
Makes you wish you had a real PDP-11/74 around... :-)
Hmm, we have several 11/70 you know. Could we build one? Or would we have to rebuild the whole cache/memory tingies?
Hehe. Yes, we have three PDP-11/70 machines.
I have two myself.
Cool. Any of them running? Between us here, we are now up to five PDP-11/70 machines. That is pretty impressive.
Update have two 11/70 in the high cabinets, and one in corporate cabinet.
Any more 11/70 machines around?
Johnny
From: Johnny Billquist <bqt at softjar.se>
The TSTSET is both a test, and a write. So it will do both. I can't
imagine that WRTLCK was to be used in combination with TSTSET.
I was picturing TSTSET for testing/acquiring a spinlock, and WRTLCK for
releasing it, but obviously other combinations could work too.
You are thinking too complex. A Qbus memory is always multiported. It's
just a slave on the bus. Any master can access it. So it is multiported.
Well OK I guess I meant multiported as it, multiple separate Q-bus interfaces
so it can be present on otherwise disjoint Q-bi.
The problem is that all CPUs think they are bus masters, and all try to
control the grant lines, which they cannot.
A little snippage would fix that part, but the problem is that CPUs won't
normally try to negotiate for bus mastership. So that's what I meant
by that -- CPU starts a bus cycle w/o warning, interface becomes bus
master on the shared Q-bus (where the memory lives) and *then* passes
the bus cycle through, hopefully before the CPU gets tired of waiting.
Wasn't it the 11/03 CPU where you could disable this by a jumper?
Sounds vaguely familiar. 11/20 too? Or was it the 11/05?
Unless the KXJ11 have some other funny stuff, such as local memory on
the card...
Beats me, I've never even seen a KXJ -- sounds like potential fun though.
OK I'll try to control myself now -- PDP-11 stuff probably isn't that
interesting to most HECnet people.
John Wilson
D Bit
Brian Hechinger wrote:
On Mon, Oct 19, 2009 at 12:31:41PM -0400, John Wilson wrote:
its behalf instead of assuming the CPU card is The Decider. I'm trying to
picture where per-CPU peripherals go in that case so the I/O page is still
private but DMA isn't ... ow my head!
If you are talking multiple CPUs on a single QBus is there much benefit to
assigning peripherals to CPUs other than CPU0? That wouldn't disallow you
to do DMA from another CPU to that peripherals I wouldn't think.
You don't do DMA from CPU to a device. Remember what DMA stands for? :-)
The benefit of assigning different devices to different CPUs are that you can balance the CPU load of the different CPUs.
For each I/O operation, the CPU have to run through the driver, which takes a non-zero amount of time. And the same is true when the I/O completes.
Hmm, I realized one thing, though. With a common Qbus, all interrupts will probably go to the bus master arbiter, which means that all devices actually must be attached to CPA, except such devices that are local to each CPU, such as the console terminal.
And in RSX speak, the CPUs are called CPA, CPB, CPC and CPD. Here is how it looks on MIM::
.con dis full att for sys
SYS SYS Online,Accpath
PDP-11/74mP, EIS,UNIBUS_Map,D-Space,SWR,Cache,FPP,
Clock=KW11-L, $TKPS=50., $TTPRM=000002
.con dis full att for cp
CPA CPA Online,Accpath
Cache_control=000001, Timer=Off, Alarm=Off
CPB CPB Offline,Accpath
Cache_control=000001, Timer=Off, Alarm=Off
CPC CPC Online,Accpath
Cache_control=000001, Timer=Off, Alarm=Off
CPD CPD Offline,Accpath
Cache_control=000001, Timer=Off, Alarm=Off
.con dis full att for du
DUA CPA Online,Accpath,Driver
Csr=172150, Vector=000154, Pri=000005, Urm=000001
DU0: CPA DUA0: Online,Accpath,Context,Driver,Type=RZ29
DU1: CPA DUA1: Online,Accpath,Driver,Type=RD53
DU2: CPA DUA2: Online,Accpath,Driver,Type=RD52
DU3: CPA DUA3: Offline,Accpath,Driver
DU4: Online,Accpath,Context,Driver,Type=VRA82
.
Notice that CPA and CPC are online.
And DUA is attached to CPA, and so on...
Johnny
Johnny Billquist wrote:
Pontus Pihlgren wrote:
Makes you wish you had a real PDP-11/74 around... :-)
Hmm, we have several 11/70 you know. Could we build one? Or would we have to rebuild the whole cache/memory tingies?
Hehe. Yes, we have three PDP-11/70 machines.
I have two myself.
Peace... Sridhar
On Mon, Oct 19, 2009 at 06:01:05PM +0200, Johnny Billquist wrote:
Well, it was just a suggestion, and one that I found easily human
readable and editable. :-)
Well, that's actually why LDIF was created the way it was. It's easily human
AND machine readable and editable.
Unlike XML, which they CLAIM is easily human readable but every time I look
at it I see red and want to stab people.
I've recently started using Apache's ANT build system. Yes, my brain hurts.
But I don't have a problem with something looking like LDIF, as long as
noone ever expects me to actually feed something into LDAP, or even use
LDAP. :-)
What do you have against LDAP? :)
-brian
--
"Coding in C is like sending a 3 year old to do groceries. You gotta
tell them exactly what you want or you'll end up with a cupboard full of
pop tarts and pancake mix." -- IRC User (http://www.bash.org/?841435)
On Mon, Oct 19, 2009 at 12:31:41PM -0400, John Wilson wrote:
its behalf instead of assuming the CPU card is The Decider. I'm trying to
picture where per-CPU peripherals go in that case so the I/O page is still
private but DMA isn't ... ow my head!
If you are talking multiple CPUs on a single QBus is there much benefit to
assigning peripherals to CPUs other than CPU0? That wouldn't disallow you
to do DMA from another CPU to that peripherals I wouldn't think.
-brian
--
"Coding in C is like sending a 3 year old to do groceries. You gotta
tell them exactly what you want or you'll end up with a cupboard full of
pop tarts and pancake mix." -- IRC User (http://www.bash.org/?841435)
John Wilson wrote:
From: Johnny Billquist <bqt at softjar.se>
Modifying RSX to use the TSTSET instead of ASRB for spin locks would be easy. It's just a macro in the sources. Not sure what WRTLCK would be used for, though. But it's been a while since I looked at these instructions, so I don't remember the details of them.
Yeah I know what you mean, how is a write not already interlocked? So I
figure what they're getting at is, TSTSET and WRTLCK are interlocked with
regard to *each other*. Well that would work anyway ...
The TSTSET is both a test, and a write. So it will do both. I can't imagine that WRTLCK was to be used in combination with TSTSET. But maybe there is something here that I don't remember right. I guess I really should go read the doc on the WRTLCK instruction. :-)
now I'm trying
to picture which is easier to design, a multi-port Q-bus memory, or some
kind of shim which isolates a CPU card and negotiates bus masterhood on
its behalf instead of assuming the CPU card is The Decider. I'm trying to
picture where per-CPU peripherals go in that case so the I/O page is still
private but DMA isn't ... ow my head!
You are thinking too complex. A Qbus memory is always multiported. It's just a slave on the bus. Any master can access it. So it is multiported. If you have several CPUs on the Qbus, all can access the memory.
The problem is that all CPUs think they are bus masters, and all try to control the grant lines, which they cannot.
Wasn't it the 11/03 CPU where you could disable this by a jumper?
Also, the KXJ11 card will play without acting as bus arbiter, so multiple of those cards would work in the same Qbus.
I wonder if anyone ever tried a KXJ11 in combination with a KDJ11? DEC only released software to have the KXJ11 as a slave to a uVAX, but I can't see a problem with having it on a Qbus with a KDJ11 master. You'd need to write some software to be able to interrupt the other CPU, but otherwise I think you'd be halfway happy.
As for peripherials, they'd be accessible by all CPUs. In the normal setup, only one CPU at a time would be logically connected to the device, though. But you'd be free to pick which one, since the Qbus is shared.
The only "private" devices would be the ones located on the CPU card, which means the console interface.
This should be doable with one 11/83 CPU, and then KXJ11s. Write an alternative to the IIST driver, and modify RSX to use the J11 instructions for spinlocks, and you should be ready to go in fact. Unless the KXJ11 have some other funny stuff, such as local memory on the card...
Johnny
On Mon, 19 Oct 2009, Sampsa Laine wrote:
Got an idea for that too :)
Make the file human readable, but have a standardised "tag line" with all the relevant data on it in a simple-to-parse format (in this case pipe | separated), e.g.
!HNINFO:1.401|CHIMPY|AlphaServer 800|OpenVMS 8.3|Comments go here|
Or something.
Here is the format I use.
=INFO MONK XP1000/667, OpenVMS 8.3
=SERVICES MONK DEC Notes Conference MONK::HOBBYIST_DECNET
=SERVICES MONK DEC Notes Conference MONK::PDP-10
=SERVICES MONK DEC Notes Conference MONK::PDP11
=SERVICES MONK DEC Notes Conference MONK::TEST
=SERVICES MONK DEC Notes Conference MONK::VMS
=INFO PDXVAX VAXstation 4000/60, VAX/VMS 5.5-2, Area Router
=SERVICES PDXVAX Guest Login
=SERVICES PDXVAX DEC Notes Client installed
=SERVICES PDXVAX Multinet Bridge to area 2
I don't actually have any need to record the node number.
Zane
From: Johnny Billquist <bqt at softjar.se>
Modifying RSX to use the TSTSET instead of ASRB for spin locks would be
easy. It's just a macro in the sources. Not sure what WRTLCK would be
used for, though. But it's been a while since I looked at these
instructions, so I don't remember the details of them.
Yeah I know what you mean, how is a write not already interlocked? So I
figure what they're getting at is, TSTSET and WRTLCK are interlocked with
regard to *each other*. Well that would work anyway ... now I'm trying
to picture which is easier to design, a multi-port Q-bus memory, or some
kind of shim which isolates a CPU card and negotiates bus masterhood on
its behalf instead of assuming the CPU card is The Decider. I'm trying to
picture where per-CPU peripherals go in that case so the I/O page is still
private but DMA isn't ... ow my head!
John Wilson
D Bit
