John Wilson wrote:
From: Brian Hechinger <wonko at 4amlunch.net>
I wonder how hard/impossible it would be to implement this entirely in an
FPGA of some sort. That would be a LOT of work, but extremely cool.
This could be a really neat project -- much easier with J11s than PDP-11/70s
though. The J11 has the TSTSET and WRTLCK interlocked instructions which
are obviously intended to take the place of the ASRB kludge on the PDP-11/74
(which is used by RSX11M+ to implement spinlocks). So you'd need some kind
of shared memory (doesn't have to emulate the MKA11 at all, shouldn't be
complicated enough to need an FPGA), and some kind of IIST emulation (which
could be mostly done with microcontrollers), and that's it. Somewhere on
the web there's a quote from one of the RSX guys which basically says that
all of this has already been done, but never released, and it was no sweat
at all.
The TSTSET and WRTLCK instructions are obviously for possible mP implementations using the J11. Also, the J11 already have the cache bypass bit implemented in the PDR.
So, in short, the J11 was already designed to be used in mP systems. All you need is just shared memory. Since early J11 machines used normal Qbus memory, the only thing you actually needed was CPU cards that didn't assume to do bus arbitration. Qbus memory is already shared.
Modifying RSX to use the TSTSET instead of ASRB for spin locks would be easy. It's just a macro in the sources. Not sure what WRTLCK would be used for, though. But it's been a while since I looked at these instructions, so I don't remember the details of them.
The quote was something like (from a DECUS session, about possible performance of multiprocessor PDP-11s):
Q: If you were to build a multiprocessor system based on J11 CPUs, how long would it take to perform a SYSGEN on such a machine?
A: It took about two hours.
I might remember the time wrong, and there might possibly also be other quotes out there, but this out implicitly admitted that they had already done it, and had a machine operational.
Johnny
From: Johnny Billquist <bqt at softjar.se>
John, did you notice that the IIST documentation now is available at
bitsavers?
I noticed that some kind of doc on the IIST showed up there shortly after I'd
spent many months tearing my remaining hair out reverse-engineering it --
skimming through it though, I couldn't find anything significant that I'd
missed (there are lots of things that RSX doesn't touch). Obviously I need
to go over it with a fine-toothed comb though ...
John Wilson
D Bit
Brian Hechinger wrote:
On Mon, Oct 19, 2009 at 05:45:27PM +0200, Johnny Billquist wrote:
Such as (just as an example):
======
HOST: MIM
HARDWARE: E11 (PDP-11/74)
OS: RSX-11M-PLUS V4.6
LOCATION: UPPSALA, SWEDEN
MANAGER: Johnny Billquist
EMAIL: bqt at update.uu.se
EMAIL: MIM::BILLQUIST
======
Keep the format simple, and very relaxed. Let software figure out if they can do anything with it or not.
Uppercase, lowercase, free flowing text. Just keep the tags standard to start with. Maybe we can have some tags with a more formalized value, if needed, such as a POS: value with LAT/LONG if people want to add that?
Hmm, that looks a LOT like an LDIF file. :)
Well, it was just a suggestion, and one that I found easily human readable and editable. :-)
But I don't have a problem with something looking like LDIF, as long as noone ever expects me to actually feed something into LDAP, or even use LDAP. :-)
Johnny
From: Brian Hechinger <wonko at 4amlunch.net>
I wonder how hard/impossible it would be to implement this entirely in an
FPGA of some sort. That would be a LOT of work, but extremely cool.
This could be a really neat project -- much easier with J11s than PDP-11/70s
though. The J11 has the TSTSET and WRTLCK interlocked instructions which
are obviously intended to take the place of the ASRB kludge on the PDP-11/74
(which is used by RSX11M+ to implement spinlocks). So you'd need some kind
of shared memory (doesn't have to emulate the MKA11 at all, shouldn't be
complicated enough to need an FPGA), and some kind of IIST emulation (which
could be mostly done with microcontrollers), and that's it. Somewhere on
the web there's a quote from one of the RSX guys which basically says that
all of this has already been done, but never released, and it was no sweat
at all.
John Wilson
D Bit
On Mon, Oct 19, 2009 at 05:45:27PM +0200, Johnny Billquist wrote:
Such as (just as an example):
======
HOST: MIM
HARDWARE: E11 (PDP-11/74)
OS: RSX-11M-PLUS V4.6
LOCATION: UPPSALA, SWEDEN
MANAGER: Johnny Billquist
EMAIL: bqt at update.uu.se
EMAIL: MIM::BILLQUIST
======
Keep the format simple, and very relaxed. Let software figure out if
they can do anything with it or not.
Uppercase, lowercase, free flowing text. Just keep the tags standard to
start with. Maybe we can have some tags with a more formalized value, if
needed, such as a POS: value with LAT/LONG if people want to add that?
Hmm, that looks a LOT like an LDIF file. :)
-brian
--
"Coding in C is like sending a 3 year old to do groceries. You gotta
tell them exactly what you want or you'll end up with a cupboard full of
pop tarts and pancake mix." -- IRC User (http://www.bash.org/?841435)
John, did you notice that the IIST documentation now is available at bitsavers?
Johnny
John Wilson wrote:
From: "Bob Armstrong" <bob at jfcl.com>
So can E11 actually use multiple processors on the host (aka Intel) side
so that the emulated 11/74 CPUs can really run in parallel?
Exactly. It also commits some atrocities (making CPUs wait for each other
while sending/receiving inter-CPU interrupts) to ensure that it'll still
basically work even on Linux/Windows systems which don't have enough
(available) 80x86 CPUs/cores to cover all the PDP-11/74 CPUs (and more
importantly, doesn't crash just because of occasional latency problems on a
heavily loaded host PC). The DOS and stand-alone versions DO need enough
80x86 CPUs though, since there's no time-slicing there (there are different
atrocities there -- all I/O is done on the boot processor since DOS and the
BIOS aren't mP-safe).
The bugginess is annoying (occasional hangs) but part of the problem is
that there are no real manuals for the IIST (the inter-processor interrupt
device) and obviously I don't have access to a real mP system to test on.
So I just did the best I could. RSX comes with sources of course, and the
IIST diag listings are in the PDP-11 fiche kit, but as always the diags
themselves mostly focus on little details (evidently the IIST used some kind
of serial bus so there's parity and other weirdness) which are hard/pointless
to emulate, and doesn't point towards whatever I'm getting wrong, so it's
not as if it's just a simple matter of ironing things out until the diag
makes it all the way through.
Anyway I would love it if more people tried out the mP feature. There's a
chapter in the Ersatz-11 manual which tells how to turn it on, and how
to configure RSX to use it. The more users, the more bug reports, and the
sooner the mP parts of E11 get all the kinks worked out. It's a lot of fun to
play with! DEC sort of pretended mP PDP-11s never happened (there was never
any official support) but only after they'd already done *all* of the work.
The mP stuff is in the real printed RSX manuals, and the diags are on the
regular XXDP packs, it's great! And lots of fun to play with...
John Wilson
D Bit
Brian Hechinger wrote:
On Mon, Oct 19, 2009 at 05:37:39PM +0200, Johnny Billquist wrote:
But all the pieces are documented, and the documents are available on the internet...
I wonder how hard/impossible it would be to implement this entirely in an
FPGA of some sort. That would be a LOT of work, but extremely cool.
Start with the basic PDP-11/70 in that case. Once you have that down, extending it to an 11/74 should be less of a problem.
I know of several attempts in the past to do PDP-11s in FPGA. I don't know if any of them have reached a working stage, but they have also been aiming a bit lower. Going for 11/40 type machines.
But it should all be doable, I think. Just given enough time and energy. :-)
Johnny
From: "Bob Armstrong" <bob at jfcl.com>
So can E11 actually use multiple processors on the host (aka Intel) side
so that the emulated 11/74 CPUs can really run in parallel?
Exactly. It also commits some atrocities (making CPUs wait for each other
while sending/receiving inter-CPU interrupts) to ensure that it'll still
basically work even on Linux/Windows systems which don't have enough
(available) 80x86 CPUs/cores to cover all the PDP-11/74 CPUs (and more
importantly, doesn't crash just because of occasional latency problems on a
heavily loaded host PC). The DOS and stand-alone versions DO need enough
80x86 CPUs though, since there's no time-slicing there (there are different
atrocities there -- all I/O is done on the boot processor since DOS and the
BIOS aren't mP-safe).
The bugginess is annoying (occasional hangs) but part of the problem is
that there are no real manuals for the IIST (the inter-processor interrupt
device) and obviously I don't have access to a real mP system to test on.
So I just did the best I could. RSX comes with sources of course, and the
IIST diag listings are in the PDP-11 fiche kit, but as always the diags
themselves mostly focus on little details (evidently the IIST used some kind
of serial bus so there's parity and other weirdness) which are hard/pointless
to emulate, and doesn't point towards whatever I'm getting wrong, so it's
not as if it's just a simple matter of ironing things out until the diag
makes it all the way through.
Anyway I would love it if more people tried out the mP feature. There's a
chapter in the Ersatz-11 manual which tells how to turn it on, and how
to configure RSX to use it. The more users, the more bug reports, and the
sooner the mP parts of E11 get all the kinks worked out. It's a lot of fun to
play with! DEC sort of pretended mP PDP-11s never happened (there was never
any official support) but only after they'd already done *all* of the work.
The mP stuff is in the real printed RSX manuals, and the diags are on the
regular XXDP packs, it's great! And lots of fun to play with...
John Wilson
D Bit
On Mon, Oct 19, 2009 at 05:37:39PM +0200, Johnny Billquist wrote:
But all the pieces are documented, and the documents are available on
the internet...
I wonder how hard/impossible it would be to implement this entirely in an
FPGA of some sort. That would be a LOT of work, but extremely cool.
-brian
--
"Coding in C is like sending a 3 year old to do groceries. You gotta
tell them exactly what you want or you'll end up with a cupboard full of
pop tarts and pancake mix." -- IRC User (http://www.bash.org/?841435)
Bob Armstrong wrote:
Why am I starting to think something like X.500 makes more sense at this
point?
There's also the format used once up on a time by the UUCP mapping project
- we have basically the same problem that they did. http://www.uucp.org/uumap/README
They're long gone now, but there are probably still lots of tools around for
processing data in this format.
Come to think of it, didn't they already have something to produce a
geographic map?
That format works, but it seems so cryptic.
What's wrong with plain text tags, followed by information
Such as (just as an example):
======
HOST: MIM
HARDWARE: E11 (PDP-11/74)
OS: RSX-11M-PLUS V4.6
LOCATION: UPPSALA, SWEDEN
MANAGER: Johnny Billquist
EMAIL: bqt at update.uu.se
EMAIL: MIM::BILLQUIST
======
Keep the format simple, and very relaxed. Let software figure out if they can do anything with it or not.
Uppercase, lowercase, free flowing text. Just keep the tags standard to start with. Maybe we can have some tags with a more formalized value, if needed, such as a POS: value with LAT/LONG if people want to add that?
I've seldom understood why people are striving for more and more complex solutions to a simple information problem. :-)
Johnny
