On 2013-01-06 03:33, John Wilson wrote: From: "Brian Schenkenberger, VAXman-" <system at TMESIS.COM> OK, I'll bite. Why is moving a character in the deferred location in R5 to the stack and then, from the stack to the address in R4 faster than just going from the deferred R5 location to the R4 address? I don't know the exact answer, but the I/O page in a PDT-11 is emulated by an 8085A and it's always super slow. I don't know why DATOB would be any worse than DATO but if DEC thought it was, I'm sure it's true (it shouldn't have to be a read-modify-write but some PDP-11 models do gratuitous extra cycles so it may well be). So this isn't actually a Q vs. U difference, it's a PDT vs. real bus difference, but the LSI-11 conditionals will catch PDTs. I know that it isn't as simple sometimes/somehow. Some devices have warnings about not doing byte operations on them, while others are fine, as far as I can remember from reading various manuals. But my memory is (as usual) fuzzy enough that I might be misremembering in one way or another. But that would suggest that doing a DATOB might not work as expected on peripherials. Most of my brain cells actually are wasted on the 11/70, where things work slightly different, since the memory bus is actually 32 bits wide. I'm probably constantly confusing the bus cycles with the memory cycles of that machine all the time. Thinking more, you are probably right that a DATOB shouldn't be a RMW cycle, but something in the PDT obviously don't like a byte write anyway. Gah. I should probably re-read the bus specs now that you got me starting to think about this again... It's been too long. Anyway, thanks Johnny! Good to know that DU and DUV are 2 for the price of 1. (And it hadn't even clicked that the thing in a PDT is emulating a DUV, so I guess it's 3 for the price of 1!) You're welcome. Johnny -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt at softjar.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol