John Wilson wrote: From: Johnny Billquist <bqt at softjar.se> Modifying RSX to use the TSTSET instead of ASRB for spin locks would be easy. It's just a macro in the sources. Not sure what WRTLCK would be used for, though. But it's been a while since I looked at these instructions, so I don't remember the details of them. Yeah I know what you mean, how is a write not already interlocked? So I figure what they're getting at is, TSTSET and WRTLCK are interlocked with regard to *each other*. Well that would work anyway ... The TSTSET is both a test, and a write. So it will do both. I can't imagine that WRTLCK was to be used in combination with TSTSET. But maybe there is something here that I don't remember right. I guess I really should go read the doc on the WRTLCK instruction. :-) now I'm trying to picture which is easier to design, a multi-port Q-bus memory, or some kind of shim which isolates a CPU card and negotiates bus masterhood on its behalf instead of assuming the CPU card is The Decider. I'm trying to picture where per-CPU peripherals go in that case so the I/O page is still private but DMA isn't ... ow my head! You are thinking too complex. A Qbus memory is always multiported. It's just a slave on the bus. Any master can access it. So it is multiported. If you have several CPUs on the Qbus, all can access the memory. The problem is that all CPUs think they are bus masters, and all try to control the grant lines, which they cannot. Wasn't it the 11/03 CPU where you could disable this by a jumper? Also, the KXJ11 card will play without acting as bus arbiter, so multiple of those cards would work in the same Qbus. I wonder if anyone ever tried a KXJ11 in combination with a KDJ11? DEC only released software to have the KXJ11 as a slave to a uVAX, but I can't see a problem with having it on a Qbus with a KDJ11 master. You'd need to write some software to be able to interrupt the other CPU, but otherwise I think you'd be halfway happy. As for peripherials, they'd be accessible by all CPUs. In the normal setup, only one CPU at a time would be logically connected to the device, though. But you'd be free to pick which one, since the Qbus is shared. The only "private" devices would be the ones located on the CPU card, which means the console interface. This should be doable with one 11/83 CPU, and then KXJ11s. Write an alternative to the IIST driver, and modify RSX to use the J11 instructions for spinlocks, and you should be ready to go in fact. Unless the KXJ11 have some other funny stuff, such as local memory on the card... Johnny