From: Brian Hechinger <wonko at 4amlunch.net> I wonder how hard/impossible it would be to implement this entirely in an FPGA of some sort. That would be a LOT of work, but extremely cool. This could be a really neat project -- much easier with J11s than PDP-11/70s though. The J11 has the TSTSET and WRTLCK interlocked instructions which are obviously intended to take the place of the ASRB kludge on the PDP-11/74 (which is used by RSX11M+ to implement spinlocks). So you'd need some kind of shared memory (doesn't have to emulate the MKA11 at all, shouldn't be complicated enough to need an FPGA), and some kind of IIST emulation (which could be mostly done with microcontrollers), and that's it. Somewhere on the web there's a quote from one of the RSX guys which basically says that all of this has already been done, but never released, and it was no sweat at all. John Wilson D Bit