Actually, the wiring is slightly more complex as the counter is reset by the bus init signal on the clr inputs, however the load signal presets the counter to a value depending on the selected polynomial. The counting in hardware is even more complex as the counter is a 1 bit binary counter combined with a 3 bit binary counter to cover the range from 8 to 12 to 16 steps clocking and varying between 10 Mhz and single stepping to develop the Done flag setting which freezes the clock generator which is a gated oscillator. But since the implementation of Simh does not follow the hardware but only replaces it with a functional equivalent, the software counting is implemented differently and then it suffices to clear the pulsecnt variable per the second proposed solution. Reindert -----Original Message----- From: Paul Koning [mailto:paulkoning@comcast.net] Sent: Wednesday, 02 February, 2022 15:44 To: Reindert Voorhorst <R.Voorhorst(a)swabhawat.com> Cc: HECnet <hecnet(a)lists.dfupdate.se> Subject: Re: [HECnet] KG11 emulation probably defective -->solved (by Paul as it is) wrote: updated code by Paul fixes the problem and yes, the diagnostics still complete without complaint. A check of the engineering drawings should verify/confirm how the pulse count is actually terminated/reset in hardware. From the manual (which reproduces a bit of the schematic in support) the more precise definition is that the counter is reset by a data register load. That would make a difference in observable behavior if single step mode is used: DONE would come on after the correct number of single step operations. I'll submit a PR with that version. Thanks Reindert for verifying the fix. paul