From: Johnny Billquist <bqt at softjar.se> Modifying RSX to use the TSTSET instead of ASRB for spin locks would be easy. It's just a macro in the sources. Not sure what WRTLCK would be used for, though. But it's been a while since I looked at these instructions, so I don't remember the details of them. Yeah I know what you mean, how is a write not already interlocked? So I figure what they're getting at is, TSTSET and WRTLCK are interlocked with regard to *each other*. Well that would work anyway ... now I'm trying to picture which is easier to design, a multi-port Q-bus memory, or some kind of shim which isolates a CPU card and negotiates bus masterhood on its behalf instead of assuming the CPU card is The Decider. I'm trying to picture where per-CPU peripherals go in that case so the I/O page is still private but DMA isn't ... ow my head! John Wilson D Bit