On Aug 10, 2010, at 5:14 PM, Johnny Billquist wrote: ... I don't think the UDA50 use any common microprocessor even, but is implemented with bitslices, and logic. Correct. The main ingredients are AMD 2901 bitslice ALUs plus a 2910 sequencer. Apparently the designer had a bunch of flexibility how those pieces go together. The UDA used a particularly interesting approach, where the micro-instruction would instruct the ALU part (2901) separate from the sequencer part (2910). The assembly language had two fields per line, one for each part. There was a one clock delay between ALU result and branch control input. So you could read odd statements like this (paraphrasing... I don't remember the exact syntax): clr r0 ; bne foo because the bne would act on the ALU output from the preceding line. I doubt that the processor part of the UDA50 would be all that hard to implement in an FPGA, but as you said, that isn't all that helpful if what you're after is MSCP support in the W11 FPGA. paul