[HECnet] Re: Weird microcode bug in the 11/60 CPU

It's funny you should mention the CDC 6600 because it was in this context that the branch remark was made. We spent /a lot/ of time studying the 6600 because of all the interesting ideas to be found there (like register score boarding, Etc.)  It was while we were discuss arithmetic performance that he pointed out the branch percentages.  What he was doing was trying force us to look at things at a systemic level instead of thinking math and he said what said not so much for accuracy but for effect. PDP-10 hackers of KA and KI vintage will immediately recognize the CDC instruction buffer as something like it was used.  The PDP-10 had sixteen registers (called accumulators or AC's) and these aliased the first sixteen locations of memory, giving you some real flexibility in instruction usage. When you /really/ needed to get speedy, you would put your instructions into the AC's and jump in.  The core memory of the day was at microsecond speeds and needed cycle time.  AC's were operating sub-microsecond time (0.21) and needed no cycle time.  So you could win pretty big. Another thing to do was to take advantage of Tops-10 giving priority to jobs with smaller memory requirements.  When WACCC (WPI) TECO had to write a file, it completely destroyed its code image (the high segment) to execute in a little AC loop to write the buffers out.  We undergraduates thought it was a very fine hack. None of this mattered on the KL because of the cache memory speed.