8 Feb
2022
8 Feb
'22
2:21 a.m.
On 2022-02-08 01:39, Paul Koning wrote:
:-)
On Feb 7, 2022, at 5:28 PM, Johnny Billquist
<bqt(a)softjar.se> wrote:
I don't think I've seen a comprehensive list of ECOs. There might be in some
microfiches, but it's been very long since I looked at those...
Maybe someone else would know if DEC ECOs are available somewhere today.
As for RSTS/E, I don't have the source to any part of RSTS/E myself, so my best bet
would be Paul. I saw he answered to this one, but completely missed (forgot?) what it was
about. Paul, you mentioned earlier that RSTS/E would give an error message at startup,
telling that it's an 11/60 CPU with the buggy microcode. This bit of code was what was
asked for.
I misunderstood. Here it is, from the first chunk of system probing code. ; THE BR BELOW MUST BE AT AN ADDRESS WITH 3 LOW DIGITS
ZERO.
. = <.-SATBUF+777+4>&177000+SATBUF-4 ;ROUND TO 4 BELOW DESIRED BOUNDARY
CHK1160:CLR @#CPUERR ;WRITE TO CPU ERROR REGISTER
.IIF NE <.-SATBUF>&777, .ERROR ;MICROCODE BUG DETECTOR REQUIRES THIS
BR NO1160 ;DIDN'T SKIP, ALL IS WELL
MESSAG ;SOME 11/60'S HAVE A PROBLEM HERE ...
.ASCII "This PDP-11/60 is missing the following ECO's:"<200>
.ASCIZ " Module M7872: ECO #7 Module M7873: ECO #6"<200><12>
UNORG
COMB (R5) ;DISALLOW WRITING TO THE REGISTER
That's interesting. It says the bug isn't simply doing a skip that isn't
supposed to happen -- it implies that the skip only happens if the PC after the
instruction is a multiple of 512. Wow.
Really interesting. RSX do not mention it, but then again, RSX just
makes sure the code is safe, which means just adding a NOP after every
write to the register if it might executed on an 11/60.
RSTS/E is definitely trying to be nicer.
But it's also interesting to see RSTS/E seems to refer to two different
ECOs: M7872-0007 (also mentioned by RSX) and M7873-0006.
Re condition codes: it depends a bit on how you define
them. There is an interesting scheme used in the Electrologica machines (X1 from 1958, X8
from 1964). Similar to ARM, they allow essentially all instructions to be executed
conditionally. Unlike ARM, you get to choose which instructions set the condition flag
and whether to set it on zero or negative or something more complicated that I always
forget. Then you can conditionally execute instructions (if flag set, or if flag clear).
You can have intervening instructions that don't touch the flag. For example:
A=VAR1,P " Load register A with VAR1, remember if it was positive
SUBC(:SUB42) " Call SUB42 to get a value in S
Y,S+VAR2 " Add VAR2 if VAR1 was positive
N,S-VAR3 " but subtract VAR3 from S
The subroutine call saves and restores (by convention, you can avoid it) the flag.
Yeah, conditional execution based on condition codes are pretty nice. I
would probably agree that they are pretty comparable to the condition
codes in the PDP-11.
That's a little different from PDP-11 condition
codes but it's close enough I think. The older machines I know do CDC or PDP-10
style "branch conditionally on the contents of a register" rather than condition
codes.
Yeah.
Johnny
--
Johnny Billquist || "I'm on a bus
|| on a psychedelic trip
email: bqt(a)softjar.se || Reading murder books
pdp is alive! || tryin' to stay hip" - B. Idol