From: Johnny Billquist <bqt at softjar.se>
The TSTSET is both a test, and a write. So it will do both. I can't
imagine that WRTLCK was to be used in combination with TSTSET.
I was picturing TSTSET for testing/acquiring a spinlock, and WRTLCK for
releasing it, but obviously other combinations could work too.
You are thinking too complex. A Qbus memory is always multiported. It's
just a slave on the bus. Any master can access it. So it is multiported.
Well OK I guess I meant multiported as it, multiple separate Q-bus interfaces
so it can be present on otherwise disjoint Q-bi.
The problem is that all CPUs think they are bus masters, and all try to
control the grant lines, which they cannot.
A little snippage would fix that part, but the problem is that CPUs won't
normally try to negotiate for bus mastership. So that's what I meant
by that -- CPU starts a bus cycle w/o warning, interface becomes bus
master on the shared Q-bus (where the memory lives) and *then* passes
the bus cycle through, hopefully before the CPU gets tired of waiting.
Wasn't it the 11/03 CPU where you could disable this by a jumper?
Sounds vaguely familiar. 11/20 too? Or was it the 11/05?
Unless the KXJ11 have some other funny stuff, such as local memory on
the card...
Beats me, I've never even seen a KXJ -- sounds like potential fun though.
OK I'll try to control myself now -- PDP-11 stuff probably isn't that
interesting to most HECnet people.
John Wilson
D Bit