[HECnet] Re: Weird microcode bug in the 11/60 CPU

Now that I've pondered the below a bit, I must say that this is a rather interesting bug.  I don't recollect hearing anything that would cause an instruction to get skipped unintentionally. The PDP-10 is interesting (or strange) in that it uses skips to convey the result of various tests and comparisons.  You don't use tests to set PC flags and do conditional jumps on them (like nearly every other architecture that comes to mind immediately). I have heard of cranky I/O hardware causing a CONSO (Conditions In and Skip if One) to think that an I/O operation was complete when it wasn't, but I don't recall a processor (which you can read conditions on) doing this.  It is true that sometimes checking an asynchronous transfer too soon can get you the wrong thing, perhaps the paradigmatic example being the PC-AT bus: TIN MACRO REG1:REQ,REG2:REQ ;; Define the macro name Local BusIdle ;; Address to Idle 286 Bus in REG1,REG2 ;; Actually do the IN jmp SHORT BusIdle ;; Basically a JMP SHORT +2 BusIdle: ; ; Target of jmp ENDM ;; End of macro The JMP SHORT functioned something like a NOP except that it hit the memory bus.  You couldn't trust anything an I/O instruction said unless you gave it time to catch up.  But the 11/60 bug isn't the same thing and I can only imagine what it took to track it down. /Very/ interesting.